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| author | Bin Meng <bmeng@tinylab.org> | 2022-11-25 13:03:54 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-01-06 10:42:55 +1000 |
| commit | bc7dca13b7ac81832c66b5dc67d0568c7b08d064 (patch) | |
| tree | 5db73d2549816b52e68e11c2b097f0a20533f6a4 /target/riscv/cpu.c | |
| parent | eacd03cb9e51f98c19dc97270c9e4745f441abbe (diff) | |
| download | focaccia-qemu-bc7dca13b7ac81832c66b5dc67d0568c7b08d064.tar.gz focaccia-qemu-bc7dca13b7ac81832c66b5dc67d0568c7b08d064.zip | |
target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()
sstatus register dump is currently missing in riscv_cpu_dump_state(). As sstatus is a copy of mstatus, which is described in the priv spec, it seems redundant to print the same information twice. Add some comments for this to let people know this is intentional. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221125050354.3166023-1-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6fe176e483..b2c132e269 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -382,6 +382,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) CSR_MHARTID, CSR_MSTATUS, CSR_MSTATUSH, + /* + * CSR_SSTATUS is intentionally omitted here as its value + * can be figured out by looking at CSR_MSTATUS + */ CSR_HSTATUS, CSR_VSSTATUS, CSR_MIP, |