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authorPaolo Bonzini <pbonzini@redhat.com>2025-02-18 11:27:12 +0100
committerPaolo Bonzini <pbonzini@redhat.com>2025-05-20 08:18:31 +0200
commit80b22be3820f1076d9de1b1f1646ae6b352d7675 (patch)
tree1d464a9e7bfba142813a2f901d413a905de6a4f7 /target/riscv/cpu.h
parentdabb54c160b84d648f375d8f7688fb1099ba32ab (diff)
downloadfocaccia-qemu-80b22be3820f1076d9de1b1f1646ae6b352d7675.tar.gz
focaccia-qemu-80b22be3820f1076d9de1b1f1646ae6b352d7675.zip
target/riscv: move satp_mode.{map,init} out of CPUConfig
They are used to provide the nice QOM properties for svNN,
but the canonical source of the CPU configuration is now
cpu->cfg.max_satp_mode.  Store them in the ArchCPU struct.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/riscv/cpu.h')
-rw-r--r--target/riscv/cpu.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3d89a4a83b..731ea2540c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -500,6 +500,19 @@ struct CPUArchState {
 };
 
 /*
+ * map is a 16-bit bitmap: the most significant set bit in map is the maximum
+ * satp mode that is supported. It may be chosen by the user and must respect
+ * what qemu implements (valid_1_10_32/64) and what the hw is capable of
+ * (supported bitmap below).
+ *
+ * init is a 16-bit bitmap used to make sure the user selected a correct
+ * configuration as per the specification.
+ */
+typedef struct {
+    uint16_t map, init;
+} RISCVSATPModes;
+
+/*
  * RISCVCPU:
  * @env: #CPURISCVState
  *
@@ -515,6 +528,7 @@ struct ArchCPU {
 
     /* Configuration Settings */
     RISCVCPUConfig cfg;
+    RISCVSATPModes satp_modes;
 
     QEMUTimer *pmu_timer;
     /* A bitmask of Available programmable counters */