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| author | Guo Ren <ren_guo@c-sky.com> | 2022-02-04 10:26:54 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-02-16 12:25:52 +1000 |
| commit | 05e6ca5e156d1d114d1eb878cae9744cb4a539e3 (patch) | |
| tree | 2e4a024c5c68f73b857957c5c3b249afd52e6a6b /target/riscv/cpu_bits.h | |
| parent | e8f79343cfc886aaa225cec9faf6881f75945209 (diff) | |
| download | focaccia-qemu-05e6ca5e156d1d114d1eb878cae9744cb4a539e3.tar.gz focaccia-qemu-05e6ca5e156d1d114d1eb878cae9744cb4a539e3.zip | |
target/riscv: Ignore reserved bits in PTE for RV64
Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual-Memory System 2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220204022658.18097-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 068c4d8034..b3489cbc10 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -565,6 +565,9 @@ typedef enum { /* Page table PPN shift amount */ #define PTE_PPN_SHIFT 10 +/* Page table PPN mask */ +#define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL + /* Leaf page shift amount */ #define PGSHIFT 12 |