diff options
| author | Fea.Wang <fea.wang@sifive.com> | 2024-12-03 11:49:29 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-12-20 11:22:47 +1000 |
| commit | 19eb69d09a3e1c3c6fef75d0679ee8b3078b82a2 (patch) | |
| tree | 964f6e145caf162097a49df37e72ea8f1230dd5f /target/riscv/cpu_bits.h | |
| parent | 81c8436277cae4d9f63a036c9241abea16ae2dc5 (diff) | |
| download | focaccia-qemu-19eb69d09a3e1c3c6fef75d0679ee8b3078b82a2.tar.gz focaccia-qemu-19eb69d09a3e1c3c6fef75d0679ee8b3078b82a2.zip | |
target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled
Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written value will be masked when the svukte extension is not enabled. When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should do svukte check. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241203034932.25185-4-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 4b9f899217..fe4e34c64a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -604,6 +604,7 @@ typedef enum { #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTW 0x00200000 #define HSTATUS_VTSR 0x00400000 +#define HSTATUS_HUKTE 0x01000000 #define HSTATUS_VSXL 0x300000000 #define HSTATUS32_WPRI 0xFF8FF87E |