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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-02-04 10:26:56 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-02-16 12:25:52 +1000 |
| commit | 2bacb22446a45b07f542d32b6d760da757233b20 (patch) | |
| tree | c82f0704c3f91cddad65bad7871cbbf424a5308e /target/riscv/cpu_bits.h | |
| parent | b6ecc63c569bb88c0fcadf79fb92bf4b88aefea8 (diff) | |
| download | focaccia-qemu-2bacb22446a45b07f542d32b6d760da757233b20.tar.gz focaccia-qemu-2bacb22446a45b07f542d32b6d760da757233b20.zip | |
target/riscv: add support for svnapot extension
- add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits = 4) Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220204022658.18097-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b3489cbc10..37ed4da72c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -561,6 +561,7 @@ typedef enum { #define PTE_A 0x040 /* Accessed */ #define PTE_D 0x080 /* Dirty */ #define PTE_SOFT 0x300 /* Reserved for Software */ +#define PTE_N 0x8000000000000000ULL /* NAPOT translation */ /* Page table PPN shift amount */ #define PTE_PPN_SHIFT 10 |