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| author | Atish Patra <atishp@rivosinc.com> | 2022-03-03 10:54:38 -0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-04-22 10:35:16 +1000 |
| commit | 3e6a417c8a077595ebcb4fb1d0944b291564cd43 (patch) | |
| tree | 567b368877681ae53ca7120bef828b91fcc87cb3 /target/riscv/cpu_bits.h | |
| parent | a4b2fa433125af0305b0695d7f8dda61db3364b0 (diff) | |
| download | focaccia-qemu-3e6a417c8a077595ebcb4fb1d0944b291564cd43.tar.gz focaccia-qemu-3e6a417c8a077595ebcb4fb1d0944b291564cd43.zip | |
target/riscv: Add support for mconfigptr
RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220303185440.512391-5-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 0fe01d7da5..48d92a81c3 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -148,6 +148,7 @@ #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 +#define CSR_MCONFIGPTR 0xf15 /* Machine Trap Setup */ #define CSR_MSTATUS 0x300 |