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| author | Atish Patra <atishp@rivosinc.com> | 2022-08-24 15:13:56 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-09-07 09:19:15 +0200 |
| commit | 43888c2f1823212b1064a6a94d65d8acaf954478 (patch) | |
| tree | f9cccb009819382f3133fe9a2516f3420fc9acb4 /target/riscv/cpu_bits.h | |
| parent | 7cbcc538f4b3040db1e39a6547efa501a8a44907 (diff) | |
| download | focaccia-qemu-43888c2f1823212b1064a6a94d65d8acaf954478.tar.gz focaccia-qemu-43888c2f1823212b1064a6a94d65d8acaf954478.zip | |
target/riscv: Add stimecmp support
stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified recently. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221357.41070-3-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6be5a9e9f0..ac17cf1515 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -206,6 +206,10 @@ #define CSR_STVAL 0x143 #define CSR_SIP 0x144 +/* Sstc supervisor CSRs */ +#define CSR_STIMECMP 0x14D +#define CSR_STIMECMPH 0x15D + /* Supervisor Protection and Translation */ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 |