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| author | LIU Zhiwei <zhiwei_liu@c-sky.com> | 2021-12-10 15:55:49 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-12-20 14:51:36 +1000 |
| commit | 61b4b69d122c055fbf6310e629f3f2d1e70c2599 (patch) | |
| tree | 584be60c06f2456326547d4d0f266b62e57552f7 /target/riscv/cpu_bits.h | |
| parent | 52561f2a808a16bde80c9a165f54e07df2e527a7 (diff) | |
| download | focaccia-qemu-61b4b69d122c055fbf6310e629f3f2d1e70c2599.tar.gz focaccia-qemu-61b4b69d122c055fbf6310e629f3f2d1e70c2599.zip | |
target/riscv: rvv-1.0: add mstatus VS field
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 9913fa9f77..72a716c999 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -375,6 +375,7 @@ #define MSTATUS_UBE 0x00000040 #define MSTATUS_MPIE 0x00000080 #define MSTATUS_SPP 0x00000100 +#define MSTATUS_VS 0x00000600 #define MSTATUS_MPP 0x00001800 #define MSTATUS_FS 0x00006000 #define MSTATUS_XS 0x00018000 |