diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2019-06-17 18:31:08 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-06-25 03:05:40 -0700 |
| commit | 747a43e818dc36bd50ef98c2b11a7c31ceb810fa (patch) | |
| tree | 13fea576f05a1532b2fdf82824a5791f36431b1c /target/riscv/cpu_bits.h | |
| parent | 6729dbbd420696fcf69cf2c86bdfc66e072058ce (diff) | |
| download | focaccia-qemu-747a43e818dc36bd50ef98c2b11a7c31ceb810fa.tar.gz focaccia-qemu-747a43e818dc36bd50ef98c2b11a7c31ceb810fa.zip | |
target/riscv: Add the mcountinhibit CSR
1.11 defines mcountinhibit, which has the same numeric CSR value as mucounteren from 1.09.1 but has different semantics. This patch enables the CSR for 1.11-based targets, which is trivial to implement because the counters in QEMU never tick (legal according to the spec). Signed-off-by: Alistair Francis <alistair.francis@wdc.com> [Palmer: Fix counter access semantics, change commit message to indicate the behavior is fully emulated.] Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 47450a3cdb..11f971ad5d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -136,6 +136,7 @@ #define CSR_MCOUNTEREN 0x306 /* Legacy Counter Setup (priv v1.9.1) */ +/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */ #define CSR_MUCOUNTEREN 0x320 #define CSR_MSCOUNTEREN 0x321 #define CSR_MHCOUNTEREN 0x322 |