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| author | Alistair Francis <alistair.francis@wdc.com> | 2020-01-31 17:01:54 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-02-27 13:45:29 -0800 |
| commit | c7b1bbc80fc2af17395d3986c346fd2307e57829 (patch) | |
| tree | efc0b420295dc152e2d5fa47dfd500a4611d6871 /target/riscv/cpu_bits.h | |
| parent | ef6bb7b62682badefdcb744831510aaa5971684f (diff) | |
| download | focaccia-qemu-c7b1bbc80fc2af17395d3986c346fd2307e57829.tar.gz focaccia-qemu-c7b1bbc80fc2af17395d3986c346fd2307e57829.zip | |
target/riscv: Add the force HS exception mode
Add a FORCE_HS_EXCEP mode to the RISC-V virtulisation status. This bit specifies if an exeption should be taken to HS mode no matter the current delegation status. This is used when an exeption must be taken to HS mode, such as when handling interrupts. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 2cdb0de4fe..ad6479796c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -432,6 +432,12 @@ /* Virtulisation Register Fields */ #define VIRT_ONOFF 1 +/* This is used to save state for when we take an exception. If this is set + * that means that we want to force a HS level exception (no matter what the + * delegation is set to). This will occur for things such as a second level + * page table fault. + */ +#define FORCE_HS_EXCEP 2 /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 |