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| author | Anup Patel <anup.patel@wdc.com> | 2022-02-04 23:16:39 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-02-16 12:24:18 +1000 |
| commit | cd032fe75c1f7b24ccad772d50bfb689e7f5835d (patch) | |
| tree | a7b62cfd8789ad2fae5409c76d32453cc1cbcac0 /target/riscv/cpu_bits.h | |
| parent | 881df35d3df52efd845087fb76d0b0116b366468 (diff) | |
| download | focaccia-qemu-cd032fe75c1f7b24ccad772d50bfb689e7f5835d.tar.gz focaccia-qemu-cd032fe75c1f7b24ccad772d50bfb689e7f5835d.zip | |
target/riscv: Implement hgeie and hgeip CSRs
The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-4-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index e1256a9982..a541705760 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -542,6 +542,7 @@ typedef enum RISCVException { #define IRQ_M_EXT 11 #define IRQ_S_GEXT 12 #define IRQ_LOCAL_MAX 16 +#define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) |