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| author | Clément Léger <cleger@rivosinc.com> | 2025-01-10 13:54:37 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-01-19 09:44:35 +1000 |
| commit | d2e92f1c6d4441221e3ae07dd24613d479b310dc (patch) | |
| tree | 8b379bc90c0a71bd91c27602d7aab18c6af30def /target/riscv/cpu_bits.h | |
| parent | b0edcbe755e88f969a5e201c093bad453ba4a13b (diff) | |
| download | focaccia-qemu-d2e92f1c6d4441221e3ae07dd24613d479b310dc.tar.gz focaccia-qemu-d2e92f1c6d4441221e3ae07dd24613d479b310dc.zip | |
target/riscv: Add Smdbltrp CSRs handling
Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior. Also set MDT to 1 at reset according to the specification. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250110125441.3208676-7-cleger@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a3acda4bc8..f97c48a394 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -559,6 +559,7 @@ #define MSTATUS_MPELP 0x020000000000 /* zicfilp */ #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL +#define MSTATUS_MDT 0x40000000000ULL /* Smdbltrp extension */ #define MSTATUS64_UXL 0x0000000300000000ULL #define MSTATUS64_SXL 0x0000000C00000000ULL |