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| author | Alexandre Ghiti <alexghiti@rivosinc.com> | 2025-07-02 07:28:52 +0000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-07-04 21:09:49 +1000 |
| commit | dc8bffc4eb0a93d3266cea1b17f8848dea5b915c (patch) | |
| tree | d9d5f76856f6e95643d46bce6c873f8eb9f38823 /target/riscv/cpu_bits.h | |
| parent | 5625817e8b77715b18d0ce3bfcc59fb337e387d8 (diff) | |
| download | focaccia-qemu-dc8bffc4eb0a93d3266cea1b17f8848dea5b915c.tar.gz focaccia-qemu-dc8bffc4eb0a93d3266cea1b17f8848dea5b915c.zip | |
target: riscv: Add Svrsw60t59b extension support
The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59 for software to use. Reviewed-by: Deepak Gupta <debug@rivosinc.com> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com> Message-ID: <20250702-dev-alex-svrsw60b59b_v2-v2-1-504ddf0f8530@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index e6b3e28386..b62dd82fe7 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -735,7 +735,8 @@ typedef enum { #define PTE_SOFT 0x300 /* Reserved for Software */ #define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */ #define PTE_N 0x8000000000000000ULL /* NAPOT translation */ -#define PTE_RESERVED 0x1FC0000000000000ULL /* Reserved bits */ +#define PTE_RESERVED(svrsw60t59b) \ + (svrsw60t59b ? 0x07C0000000000000ULL : 0x1FC0000000000000ULL) /* Reserved bits */ #define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */ /* Page table PPN shift amount */ |