diff options
| author | Kaiwen Xue <kaiwenx@rivosinc.com> | 2025-01-10 00:21:34 -0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-01-19 09:44:35 +1000 |
| commit | e84af935607e3df409cbf0854bc4f4a1b828ce76 (patch) | |
| tree | 072e8bf6e5a9e99ad76caf6d740dbeae8af8a824 /target/riscv/cpu_bits.h | |
| parent | f2548886b3dff228b82e91808553616c4b8d14a8 (diff) | |
| download | focaccia-qemu-e84af935607e3df409cbf0854bc4f4a1b828ce76.tar.gz focaccia-qemu-e84af935607e3df409cbf0854bc4f4a1b828ce76.zip | |
target/riscv: Add counter delegation definitions
This adds definitions for counter delegation, including the new scountinhibit register and the mstateen.CD bit. Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-ID: <20250110-counter_delegation-v5-6-e83d797ae294@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6b1446fb7e..73f7d37d80 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -210,6 +210,9 @@ #define CSR_SSTATEEN2 0x10E #define CSR_SSTATEEN3 0x10F +/* Supervisor Counter Delegation */ +#define CSR_SCOUNTINHIBIT 0x120 + /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 @@ -779,6 +782,7 @@ typedef enum RISCVException { #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) #define MENVCFG_PMM (3ULL << 32) +#define MENVCFG_CDE (1ULL << 60) #define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) @@ -826,7 +830,9 @@ typedef enum RISCVException { #define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 #define ISELECT_MASK_AIA 0x1ff -/* MISELECT, SISELECT, and VSISELECT bits (AIA) */ +/* [M|S|VS]SELCT value for Indirect CSR Access Extension */ +#define ISELECT_CD_FIRST 0x40 +#define ISELECT_CD_LAST 0x5f #define ISELECT_MASK_SXCSRIND 0xfff /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ |