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| author | Markus Armbruster <armbru@redhat.com> | 2019-06-04 20:16:18 +0200 |
|---|---|---|
| committer | Markus Armbruster <armbru@redhat.com> | 2019-06-12 13:20:21 +0200 |
| commit | f91005e195e7e1485e60cb121731589960f1a3c9 (patch) | |
| tree | e734135671b02f0c6bbf5785006401843e925a06 /target/riscv/cpu_bits.h | |
| parent | 37677d7db39a3c250ad661d00fb7c3b59d047b1f (diff) | |
| download | focaccia-qemu-f91005e195e7e1485e60cb121731589960f1a3c9.tar.gz focaccia-qemu-f91005e195e7e1485e60cb121731589960f1a3c9.zip | |
Supply missing header guards
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190604181618.19980-5-armbru@redhat.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index dc9d53d4be..47450a3cdb 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -1,5 +1,8 @@ /* RISC-V ISA constants */ +#ifndef TARGET_RISCV_CPU_BITS_H +#define TARGET_RISCV_CPU_BITS_H + #define get_field(reg, mask) (((reg) & \ (target_ulong)(mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \ @@ -527,3 +530,5 @@ #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP #define SIP_SEIP MIP_SEIP + +#endif |