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| author | Claudio Fontana <cfontana@suse.de> | 2021-02-04 17:39:18 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-02-05 10:24:14 -1000 |
| commit | cbc183d2d9f5b8a33c2a6cf9cb242b04db1e8d5c (patch) | |
| tree | c9e34796f87ca99c40721955da1c569c2275ff06 /target/riscv/cpu_helper.c | |
| parent | 0545608056a6161e7020cd7b9368d9636fa80051 (diff) | |
| download | focaccia-qemu-cbc183d2d9f5b8a33c2a6cf9cb242b04db1e8d5c.tar.gz focaccia-qemu-cbc183d2d9f5b8a33c2a6cf9cb242b04db1e8d5c.zip | |
cpu: move cc->transaction_failed to tcg_ops
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [claudio: wrap target code around CONFIG_TCG and !CONFIG_USER_ONLY] avoiding its use in headers used by common_ss code (should be poisoned). Note: need to be careful with the use of CONFIG_USER_ONLY, Message-Id: <20210204163931.7358-11-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/riscv/cpu_helper.c')
| -rw-r--r-- | target/riscv/cpu_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f8350f5f78..2f43939fb6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -671,7 +671,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, env->badaddr = addr; riscv_raise_exception(env, cs->exception_index, retaddr); } -#endif +#endif /* !CONFIG_USER_ONLY */ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, |