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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-05 16:58:13 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | 246f87960a22d293ab4033bdfee3d4258494ec9b (patch) | |
| tree | e1ddb6ba66576404ad4e1bb6f794f23263c6ae80 /target/riscv/debug.c | |
| parent | 3b57254d8a61497e21bfbe635c7a2dba4ece12dc (diff) | |
| download | focaccia-qemu-246f87960a22d293ab4033bdfee3d4258494ec9b.tar.gz focaccia-qemu-246f87960a22d293ab4033bdfee3d4258494ec9b.zip | |
target/riscv: Fix lines with over 80 characters
Fix lines with over 80 characters for both code and comments. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230405085813.40643-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/debug.c')
| -rw-r--r-- | target/riscv/debug.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 1f7aed23c9..75ee1c4971 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -282,8 +282,8 @@ static target_ulong type2_mcontrol_validate(CPURISCVState *env, /* validate size encoding */ size = type2_breakpoint_size(env, ctrl); if (access_size[size] == -1) { - qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n", - size); + qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using " + "SIZE_ANY\n", size); } else { val |= (ctrl & TYPE2_SIZELO); if (riscv_cpu_mxl(env) == MXL_RV64) { @@ -411,8 +411,8 @@ static target_ulong type6_mcontrol6_validate(CPURISCVState *env, /* validate size encoding */ size = extract32(ctrl, 16, 4); if (access_size[size] == -1) { - qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n", - size); + qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using " + "SIZE_ANY\n", size); } else { val |= (ctrl & TYPE6_SIZE); } @@ -696,7 +696,8 @@ target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index) int trigger_type; switch (tdata_index) { case TDATA1: - trigger_type = extract_trigger_type(env, env->tdata1[env->trigger_cur]); + trigger_type = extract_trigger_type(env, + env->tdata1[env->trigger_cur]); if ((trigger_type == TRIGGER_TYPE_INST_CNT) && icount_enabled()) { return deposit64(env->tdata1[env->trigger_cur], 10, 14, itrigger_get_adjust_count(env)); |