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| author | Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> | 2022-06-02 17:52:46 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-06-10 09:31:42 +1000 |
| commit | d1d8541217ce8a23e9e751cd868c7d618817134a (patch) | |
| tree | 6fcbd3878912245887db672f939bfae66e24c9e4 /target/riscv/debug.c | |
| parent | 8f42415fc1d1bb462f2001bf5e2ad3b78f14b2e3 (diff) | |
| download | focaccia-qemu-d1d8541217ce8a23e9e751cd868c7d618817134a.tar.gz focaccia-qemu-d1d8541217ce8a23e9e751cd868c7d618817134a.zip | |
target/riscv/debug.c: keep experimental rv128 support working
Add an MXL_RV128 case in two switches so that no error is triggered when using the -cpu x-rv128 option. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220602155246.38837-1-frederic.petrot@univ-grenoble-alpes.fr> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/debug.c')
| -rw-r--r-- | target/riscv/debug.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 2f2a51c732..fc6e13222f 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -77,6 +77,7 @@ static inline target_ulong trigger_type(CPURISCVState *env, tdata1 = RV32_TYPE(type); break; case MXL_RV64: + case MXL_RV128: tdata1 = RV64_TYPE(type); break; default: @@ -123,6 +124,7 @@ static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val, tdata1 = RV32_TYPE(t); break; case MXL_RV64: + case MXL_RV128: type = extract64(val, 60, 4); dmode = extract64(val, 59, 1); tdata1 = RV64_TYPE(t); |