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| author | Frank Chang <frank.chang@sifive.com> | 2022-09-09 21:42:12 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-09-27 11:23:57 +1000 |
| commit | 31b9798d824512b7daf868cc8581f9a97a9d13a8 (patch) | |
| tree | 804cae03acad52a5795b94ebbfb347c54d6be298 /target/riscv/debug.h | |
| parent | 6ea8d3fc40a8db8d22d00255cea9f9f8c927d643 (diff) | |
| download | focaccia-qemu-31b9798d824512b7daf868cc8581f9a97a9d13a8.tar.gz focaccia-qemu-31b9798d824512b7daf868cc8581f9a97a9d13a8.zip | |
target/riscv: debug: Introduce tinfo CSR
tinfo.info: One bit for each possible type enumerated in tdata1. If the bit is set, then that type is supported by the currently selected trigger. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20220909134215.1843865-6-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/debug.h')
| -rw-r--r-- | target/riscv/debug.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 76146f373a..9f69c64591 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -95,6 +95,8 @@ void tselect_csr_write(CPURISCVState *env, target_ulong val); target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val); +target_ulong tinfo_csr_read(CPURISCVState *env); + void riscv_cpu_debug_excp_handler(CPUState *cs); bool riscv_cpu_debug_check_breakpoint(CPUState *cs); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); |