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| author | Frank Chang <frank.chang@sifive.com> | 2022-09-09 21:42:10 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-09-27 11:23:57 +1000 |
| commit | 9495c4888a80809ab9dba6d6e536b21c018c77a4 (patch) | |
| tree | 11f02f09ff1abbb2fef701bf75e5a5f173f79a3c /target/riscv/debug.h | |
| parent | 9d5a84db91f12bd843206a57e0cde01e6a9d488d (diff) | |
| download | focaccia-qemu-9495c4888a80809ab9dba6d6e536b21c018c77a4.tar.gz focaccia-qemu-9495c4888a80809ab9dba6d6e536b21c018c77a4.zip | |
target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
Replace type2_trigger_t with the real tdata1, tdata2, and tdata3 CSRs, which allows us to support more types of triggers in the future. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20220909134215.1843865-4-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/debug.h')
| -rw-r--r-- | target/riscv/debug.h | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/target/riscv/debug.h b/target/riscv/debug.h index c422553c27..76146f373a 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -44,13 +44,6 @@ typedef enum { TRIGGER_TYPE_NUM } trigger_type_t; -typedef struct { - target_ulong mcontrol; - target_ulong maddress; - struct CPUBreakpoint *bp; - struct CPUWatchpoint *wp; -} type2_trigger_t; - /* tdata1 field masks */ #define RV32_TYPE(t) ((uint32_t)(t) << 28) |