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| author | Frank Chang <frank.chang@sifive.com> | 2022-09-09 21:42:15 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-09-27 11:23:57 +1000 |
| commit | c472c142a7552f5b0e40378d5643a2810ef1b111 (patch) | |
| tree | f791e17cc0b025d19b55539516ff1a857a5ed753 /target/riscv/debug.h | |
| parent | c32461d8eeb17490b1b1e969e2ce8f1ecd83bfbb (diff) | |
| download | focaccia-qemu-c472c142a7552f5b0e40378d5643a2810ef1b111.tar.gz focaccia-qemu-c472c142a7552f5b0e40378d5643a2810ef1b111.zip | |
target/riscv: debug: Add initial support of type 6 trigger
Type 6 trigger is similar to a type 2 trigger, but provides additional functionality and should be used instead of type 2 in newer implementations. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220909134215.1843865-9-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/debug.h')
| -rw-r--r-- | target/riscv/debug.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 0e4859cf74..a1226b4d29 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -85,6 +85,24 @@ typedef enum { #define TYPE2_HIT BIT(20) #define TYPE2_SIZEHI (0x3 << 21) /* RV64 only */ +/* mcontrol6 field masks */ + +#define TYPE6_LOAD BIT(0) +#define TYPE6_STORE BIT(1) +#define TYPE6_EXEC BIT(2) +#define TYPE6_U BIT(3) +#define TYPE6_S BIT(4) +#define TYPE6_M BIT(6) +#define TYPE6_MATCH (0xf << 7) +#define TYPE6_CHAIN BIT(11) +#define TYPE6_ACTION (0xf << 12) +#define TYPE6_SIZE (0xf << 16) +#define TYPE6_TIMING BIT(20) +#define TYPE6_SELECT BIT(21) +#define TYPE6_HIT BIT(22) +#define TYPE6_VU BIT(23) +#define TYPE6_VS BIT(24) + /* access size */ enum { SIZE_ANY = 0, |