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| author | Paolo Bonzini <pbonzini@redhat.com> | 2025-02-06 13:13:23 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2025-05-20 08:18:53 +0200 |
| commit | 5fd23f20e12a56e7ac2dabbe9570fb2f10d7c5b4 (patch) | |
| tree | 36f5337db1d440bde02e71f98abac5bfc452925f /target/riscv/gdbstub.c | |
| parent | 71fb3aa5ebba5ba822371f864a12dbcded08147d (diff) | |
| download | focaccia-qemu-5fd23f20e12a56e7ac2dabbe9570fb2f10d7c5b4.tar.gz focaccia-qemu-5fd23f20e12a56e7ac2dabbe9570fb2f10d7c5b4.zip | |
target/riscv: store RISCVCPUDef struct directly in the class
Prepare for adding more fields to RISCVCPUDef and reading them in riscv_cpu_init: instead of storing the misa_mxl_max field in RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct and go through it. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/riscv/gdbstub.c')
| -rw-r--r-- | target/riscv/gdbstub.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 18e88f416a..1934f919c0 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -62,7 +62,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) return 0; } - switch (mcc->misa_mxl_max) { + switch (mcc->def->misa_mxl_max) { case MXL_RV32: return gdb_get_reg32(mem_buf, tmp); case MXL_RV64: @@ -82,7 +82,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) int length = 0; target_ulong tmp; - switch (mcc->misa_mxl_max) { + switch (mcc->def->misa_mxl_max) { case MXL_RV32: tmp = (int32_t)ldl_p(mem_buf); length = 4; @@ -359,7 +359,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs), 0); } - switch (mcc->misa_mxl_max) { + switch (mcc->def->misa_mxl_max) { case MXL_RV32: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, |