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| author | Jim Shu <jim.shu@sifive.com> | 2025-09-24 15:48:18 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-10-03 13:15:14 +1000 |
| commit | 0b16c7b6a854d461cdfd418769b51d58e43dd92a (patch) | |
| tree | 600387b41fefc65e44ebcb45b06dc9e3a94fe755 /target/riscv/helper.h | |
| parent | 84c1605b7606d810ded4c1c3a2717f158dc89e3f (diff) | |
| download | focaccia-qemu-0b16c7b6a854d461cdfd418769b51d58e43dd92a.tar.gz focaccia-qemu-0b16c7b6a854d461cdfd418769b51d58e43dd92a.zip | |
target/riscv: Fix ssamoswap error handling
Follow the RISC-V CFI v1.0 spec [1] to fix the exception type when ssamoswap is disabled by xSSE. [1] RISC-V CFI spec v1.0, ch2.7 Atomic Swap from a Shadow Stack Location Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250924074818.230010-4-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/helper.h')
| -rw-r--r-- | target/riscv/helper.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/helper.h b/target/riscv/helper.h index f712b1c368..c82bacdc39 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1284,3 +1284,8 @@ DEF_HELPER_4(vgmul_vv, void, ptr, ptr, env, i32) DEF_HELPER_5(vsm4k_vi, void, ptr, ptr, i32, env, i32) DEF_HELPER_4(vsm4r_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32) + +/* CFI (zicfiss) helpers */ +#ifndef CONFIG_USER_ONLY +DEF_HELPER_1(ssamoswap_disabled, void, env) +#endif |