summary refs log tree commit diff stats
path: root/target/riscv/op_helper.c
diff options
context:
space:
mode:
authorMichael Clark <mjc@sifive.com>2018-04-06 12:46:19 +1200
committerMichael Clark <mjc@sifive.com>2018-05-06 10:39:38 +1200
commit6fce529c4b3ecbff17bbd930f6beaac9a6067114 (patch)
tree5254f5e326c722b518b78791aec540628ddb95b4 /target/riscv/op_helper.c
parent8c59f5c1b5aabbad92871bf62bb302fef017e322 (diff)
downloadfocaccia-qemu-6fce529c4b3ecbff17bbd930f6beaac9a6067114.tar.gz
focaccia-qemu-6fce529c4b3ecbff17bbd930f6beaac9a6067114.zip
RISC-V: Add mcycle/minstret support for -icount auto
Previously the mycycle/minstret CSRs and rdcycle/rdinstret
psuedo instructions would return the time as a proxy for an
increasing instruction counter in the absence of having a
precise instruction count. If QEMU is invoked with -icount,
the mcycle/minstret CSRs and rdcycle/rdinstret psuedo
instructions will return the instruction count.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/op_helper.c')
-rw-r--r--target/riscv/op_helper.c28
1 files changed, 26 insertions, 2 deletions
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 7416412b18..3512462f4f 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -434,25 +434,49 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
     case CSR_INSTRET:
     case CSR_CYCLE:
         if (ctr_ok) {
+#if !defined(CONFIG_USER_ONLY)
+            if (use_icount) {
+                return cpu_get_icount();
+            } else {
+                return cpu_get_host_ticks();
+            }
+#else
             return cpu_get_host_ticks();
+#endif
         }
         break;
 #if defined(TARGET_RISCV32)
     case CSR_INSTRETH:
     case CSR_CYCLEH:
         if (ctr_ok) {
+#if !defined(CONFIG_USER_ONLY)
+            if (use_icount) {
+                return cpu_get_icount() >> 32;
+            } else {
+                return cpu_get_host_ticks() >> 32;
+            }
+#else
             return cpu_get_host_ticks() >> 32;
+#endif
         }
         break;
 #endif
 #ifndef CONFIG_USER_ONLY
     case CSR_MINSTRET:
     case CSR_MCYCLE:
-        return cpu_get_host_ticks();
+        if (use_icount) {
+            return cpu_get_icount();
+        } else {
+            return cpu_get_host_ticks();
+        }
     case CSR_MINSTRETH:
     case CSR_MCYCLEH:
 #if defined(TARGET_RISCV32)
-        return cpu_get_host_ticks() >> 32;
+        if (use_icount) {
+            return cpu_get_icount() >> 32;
+        } else {
+            return cpu_get_host_ticks() >> 32;
+        }
 #endif
         break;
     case CSR_MUCOUNTEREN: