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| author | LIU Zhiwei <zhiwei_liu@c-sky.com> | 2022-01-20 20:20:37 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:57 +1000 |
| commit | 83b519b8a44d6b7d9b9d9763e7189061e116215d (patch) | |
| tree | a28937805f66159e8e2eb1b10e95e81d437d3367 /target/riscv/op_helper.c | |
| parent | 47bdec821b8dda7658e3e802a26b9bd8319cdb49 (diff) | |
| download | focaccia-qemu-83b519b8a44d6b7d9b9d9763e7189061e116215d.tar.gz focaccia-qemu-83b519b8a44d6b7d9b9d9763e7189061e116215d.zip | |
target/riscv: Adjust csr write mask with XLEN
Write mask is representing the bits we care about. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-11-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/op_helper.c')
| -rw-r--r-- | target/riscv/op_helper.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 67693cb42b..1a75ba11e6 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -50,7 +50,8 @@ target_ulong helper_csrr(CPURISCVState *env, int csr) void helper_csrw(CPURISCVState *env, int csr, target_ulong src) { - RISCVException ret = riscv_csrrw(env, csr, NULL, src, -1); + target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1; + RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask); if (ret != RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); |