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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2022-02-07 13:35:58 +0100
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2022-03-06 22:23:09 +0100
commit1ea4a06af0f6578e5d0ddcea148503290b1c4907 (patch)
tree060b35cfbdf984ec058efb07d1815283b1058dd0 /target/rx/cpu.h
parent36861198754af7577c73cdb19e1e385c933bfdc8 (diff)
downloadfocaccia-qemu-1ea4a06af0f6578e5d0ddcea148503290b1c4907.tar.gz
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target: Use CPUArchState as interface to target-specific CPU state
While CPUState is our interface with generic code, CPUArchState is
our interface with target-specific code. Use CPUArchState as an
abstract type, defined by each target.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220214183144.27402-13-f4bug@amsat.org>
Diffstat (limited to 'target/rx/cpu.h')
-rw-r--r--target/rx/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 58adf9edf6..0f3d9d5bd9 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -65,7 +65,7 @@ enum {
     NUM_REGS = 16,
 };
 
-typedef struct CPURXState {
+typedef struct CPUArchState {
     /* CPU registers */
     uint32_t regs[NUM_REGS];    /* general registers */
     uint32_t psw_o;             /* O bit of status register */