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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-12-17 14:12:52 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-12-17 14:12:52 +0000 |
| commit | 55745005e90a9deabd3d7900e13fc850f26f9d62 (patch) | |
| tree | c9218bd598fd2a7644b27a03c0c05dbed5c1f62d /target/sparc | |
| parent | d038d2645acabf6f52fd61baeaa021c3ebe97714 (diff) | |
| parent | a0c2e80afc98a9771b109eb5ce0b47edd7c78155 (diff) | |
| download | focaccia-qemu-55745005e90a9deabd3d7900e13fc850f26f9d62.tar.gz focaccia-qemu-55745005e90a9deabd3d7900e13fc850f26f9d62.zip | |
Merge tag 'pull-target-arm-20221216' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
reset refactoring queue: * remove uses of qdev_reset_all(), qbus_reset_all(), device_legacy_reset() * convert various devices to 3-phase reset, so we can remove their uses of device_class_set_parent_reset() # gpg: Signature made Fri 16 Dec 2022 21:41:11 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20221216' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) hw/pci-host/pnv_phb3_msi: Convert TYPE_PHB3_MSI to 3-phase reset hw/intc/xics: Convert TYPE_ICS to 3-phase reset hw/intc/xics: Reset TYPE_ICS objects with device_cold_reset() pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase reset pci: Convert TYPE_PCIE_ROOT_PORT to 3-phase reset hw/display/virtio-vga: Convert TYPE_VIRTIO_VGA_BASE to 3-phase reset hw/virtio: Convert TYPE_VIRTIO_PCI to 3-phase reset target/xtensa: Convert to 3-phase reset target/tricore: Convert to 3-phase reset target/sparc: Convert to 3-phase reset target/sh4: Convert to 3-phase reset target/rx: Convert to 3-phase reset target/riscv: Convert to 3-phase reset target/ppc: Convert to 3-phase reset target/openrisc: Convert to 3-phase reset target/nios2: Convert to 3-phase reset target/mips: Convert to 3-phase reset target/microblaze: Convert to 3-phase reset target/m68k: Convert to 3-phase reset target/loongarch: Convert to 3-phase reset ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/sparc')
| -rw-r--r-- | target/sparc/cpu-qom.h | 4 | ||||
| -rw-r--r-- | target/sparc/cpu.c | 12 |
2 files changed, 10 insertions, 6 deletions
diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index 86ed37d933..78bf00b9a2 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -35,7 +35,7 @@ typedef struct sparc_def_t sparc_def_t; /** * SPARCCPUClass: * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. + * @parent_phases: The parent class' reset phase handlers. * * A SPARC CPU model. */ @@ -45,7 +45,7 @@ struct SPARCCPUClass { /*< public >*/ DeviceRealize parent_realize; - DeviceReset parent_reset; + ResettablePhases parent_phases; sparc_def_t *cpu_def; }; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 4c3d08a875..1734ef8dc6 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -28,14 +28,16 @@ //#define DEBUG_FEATURES -static void sparc_cpu_reset(DeviceState *dev) +static void sparc_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(dev); + CPUState *s = CPU(obj); SPARCCPU *cpu = SPARC_CPU(s); SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu); CPUSPARCState *env = &cpu->env; - scc->parent_reset(dev); + if (scc->parent_phases.hold) { + scc->parent_phases.hold(obj); + } memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); env->cwp = 0; @@ -889,12 +891,14 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); device_class_set_parent_realize(dc, sparc_cpu_realizefn, &scc->parent_realize); device_class_set_props(dc, sparc_cpu_properties); - device_class_set_parent_reset(dc, sparc_cpu_reset, &scc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL, + &scc->parent_phases); cc->class_by_name = sparc_cpu_class_by_name; cc->parse_features = sparc_cpu_parse_features; |