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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-03-15 15:34:27 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-03-15 15:34:27 +0000 |
| commit | 51204c2f188ec1e2a38f14718d38a3772f850a4b (patch) | |
| tree | 47aae10b9baf4b79383be658168f70c446ed501d /target/tricore/helper.c | |
| parent | 36d840f35b4fc7e2d47fb54313950f82690b2286 (diff) | |
| parent | a21993c7f98862823280d1eb6d3e93cf6267896f (diff) | |
| download | focaccia-qemu-51204c2f188ec1e2a38f14718d38a3772f850a4b.tar.gz focaccia-qemu-51204c2f188ec1e2a38f14718d38a3772f850a4b.zip | |
Merge remote-tracking branch 'remotes/bkoppelmann2/tags/pull-tricore-20210314' into staging
- Added triboard with tc27x_soc - Cleaned up get_physical_address() - Fixed corner case bugs in OPC2_32_RRPW_IMASK and OPC2_32_RRPW_IMASK insns # gpg: Signature made Sun 14 Mar 2021 13:53:11 GMT # gpg: using RSA key 6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14 # gpg: issuer "kbastian@mail.uni-paderborn.de" # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" [full] # Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E 6E37 0AD2 C639 6B69 CA14 * remotes/bkoppelmann2/tags/pull-tricore-20210314: target/tricore: Fix OPC2_32_RRPW_EXTR for width=0 target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2 tricore: fixed faulty conditions for extr and imask target/tricore: Remove unused definitions target/tricore: Pass MMUAccessType to get_physical_address() target/tricore: Replace magic value by MMU_DATA_LOAD definition tricore: added triboard with tc27x_soc Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/tricore/helper.c')
| -rw-r--r-- | target/tricore/helper.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7715293263..c5e997f321 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -33,7 +33,7 @@ enum { #if defined(CONFIG_SOFTMMU) static int get_physical_address(CPUTriCoreState *env, hwaddr *physical, int *prot, target_ulong address, - int rw, int access_type) + MMUAccessType access_type, int mmu_idx) { int ret = TLBRET_MATCH; @@ -50,7 +50,8 @@ hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) int prot; int mmu_idx = cpu_mmu_index(&cpu->env, false); - if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) { + if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, + MMU_DATA_LOAD, mmu_idx)) { return -1; } return phys_addr; @@ -71,13 +72,11 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, CPUTriCoreState *env = &cpu->env; hwaddr physical; int prot; - int access_type; int ret = 0; rw &= 1; - access_type = ACCESS_INT; ret = get_physical_address(env, &physical, &prot, - address, rw, access_type); + address, rw, mmu_idx); qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n", |