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| author | Michael Tokarev <mjt@tls.msk.ru> | 2023-11-14 19:09:54 +0300 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-11-15 11:59:54 +0300 |
| commit | 385b3280ce755448e95d4376d514b3ae001931db (patch) | |
| tree | b2aa5bbdcababc9c9ca91847c61634026b9ef0a4 /target | |
| parent | 51464c5612a0a389b1a9abb99b3a6a84f6ddc42f (diff) | |
| download | focaccia-qemu-385b3280ce755448e95d4376d514b3ae001931db.tar.gz focaccia-qemu-385b3280ce755448e95d4376d514b3ae001931db.zip | |
target/hppa: spelling fixes: Indicies, Truely
Fixes: bb67ec32a0bb "target/hppa: Include PSW_P in tb flags and mmu index" Fixes: d7553f3591bb "target/hppa: Populate an interval tree with valid tlb entries" Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'target')
| -rw-r--r-- | target/hppa/cpu.h | 2 | ||||
| -rw-r--r-- | target/hppa/machine.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index bcfed04f7c..8be45c69c9 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -56,7 +56,7 @@ 1 << MMU_PL2_IDX | 1 << MMU_PL2_P_IDX | \ 1 << MMU_USER_IDX | 1 << MMU_USER_P_IDX) -/* Indicies to flush for access_id changes. */ +/* Indices to flush for access_id changes. */ #define HPPA_MMU_FLUSH_P_MASK \ (1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX | \ 1 << MMU_PL2_P_IDX | 1 << MMU_USER_P_IDX) diff --git a/target/hppa/machine.c b/target/hppa/machine.c index 2f8e8cc5a1..15cbc5e6d0 100644 --- a/target/hppa/machine.c +++ b/target/hppa/machine.c @@ -129,7 +129,7 @@ static int tlb_post_load(void *opaque, int version_id) /* * Re-create the interval tree from the valid entries. - * Truely invalid entries should have start == end == 0. + * Truly invalid entries should have start == end == 0. * Otherwise it should be the in-flight tlb_partial entry. */ for (uint32_t i = 0; i < ARRAY_SIZE(env->tlb); ++i) { |