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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-07-13 15:14:48 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-07-13 15:14:48 +0100 |
| commit | 5c65b1f135ff09d24827fa3a17e56a4f8a032cd5 (patch) | |
| tree | 5fd2ae411557b99697ca46f2a46d6fd7f21de3b0 /target | |
| parent | 00ce6c36b35e0eb8cc5d68a28f288a6335848813 (diff) | |
| parent | 756f739b1682bf131994ec96dad7fbdf8b54493a (diff) | |
| download | focaccia-qemu-5c65b1f135ff09d24827fa3a17e56a4f8a032cd5.tar.gz focaccia-qemu-5c65b1f135ff09d24827fa3a17e56a4f8a032cd5.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200713' into staging
target-arm queue: * hw/arm/bcm2836: Remove unused 'cpu_type' field * target/arm: Fix mtedesc for do_mem_zpz * Add the ability to change the FEC PHY MDIO device number on i.MX25/i.MX6/i.MX7 * target/arm: Don't do raw writes for PMINTENCLR * virtio-iommu: Fix coverity issue in virtio_iommu_handle_command() * build: Fix various issues with building on Haiku * target/nios2: fix wrctl behaviour when using icount * hw/arm/tosa: Encapsulate misc GPIO handling in a device * hw/arm/palm.c: Encapsulate misc GPIO handling in a device * hw/arm/aspeed: Do not create and attach empty SD cards by default # gpg: Signature made Mon 13 Jul 2020 15:08:16 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200713: (25 commits) hw/arm/aspeed: Do not create and attach empty SD cards by default hw/arm/palm.c: Encapsulate misc GPIO handling in a device hw/arm/palm.c: Detabify hw/arm/tosa: Encapsulate misc GPIO handling in a device hw/arm/tosa.c: Detabify hw/nios2: exit to main CPU loop only when unmasking interrupts target/nios2: Use gen_io_start around wrctl instruction target/nios2: in line the semantics of DISAS_UPDATE with other targets target/nios2: add DISAS_NORETURN case for nothing more to generate util/drm: make portable by avoiding struct dirent d_type util/oslib-posix.c: Implement qemu_init_exec_dir() for Haiku util/compatfd.c: Only include <sys/syscall.h> if CONFIG_SIGNALFD bswap.h: Include <endian.h> on Haiku for bswap operations osdep.h: For Haiku, define SIGIO as equivalent to SIGPOLL osdep.h: Always include <sys/signal.h> if it exists build: Check that mlockall() exists util/qemu-openpty.c: Don't assume pty.h is glibc-only build: Enable BSD symbols for Haiku virtio-iommu: Fix coverity issue in virtio_iommu_handle_command() target/arm: Don't do raw writes for PMINTENCLR ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/helper.c | 4 | ||||
| -rw-r--r-- | target/arm/translate-sve.c | 2 | ||||
| -rw-r--r-- | target/nios2/translate.c | 12 |
3 files changed, 12 insertions, 6 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index dc9c29f998..c69a2baf1d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2269,13 +2269,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .resetvalue = 0x0 }, { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .accessfn = access_tpm, - .type = ARM_CP_ALIAS | ARM_CP_IO, + .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .writefn = pmintenclr_write, }, { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, .access = PL1_RW, .accessfn = access_tpm, - .type = ARM_CP_ALIAS | ARM_CP_IO, + .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .writefn = pmintenclr_write }, { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 08f0fd15b2..88a2fb271d 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5275,7 +5275,7 @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz); desc <<= SVE_MTEDESC_SHIFT; } - desc = simd_desc(vsz, vsz, scale); + desc = simd_desc(vsz, vsz, desc | scale); t_desc = tcg_const_i32(desc); tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 6c34cd3193..9824544eb3 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -32,6 +32,7 @@ #include "exec/cpu_ldst.h" #include "exec/translator.h" #include "qemu/qemu-print.h" +#include "exec/gen-icount.h" /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ @@ -149,7 +150,7 @@ static void t_gen_helper_raise_exception(DisasContext *dc, tcg_gen_movi_tl(dc->cpu_R[R_PC], dc->pc); gen_helper_raise_exception(dc->cpu_env, tmp); tcg_temp_free_i32(tmp); - dc->is_jmp = DISAS_UPDATE; + dc->is_jmp = DISAS_NORETURN; } static bool use_goto_tb(DisasContext *dc, uint32_t dest) @@ -518,7 +519,11 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) /* If interrupts were enabled using WRCTL, trigger them. */ #if !defined(CONFIG_USER_ONLY) if ((instr.imm5 + CR_BASE) == CR_STATUS) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_check_interrupts(dc->cpu_env); + dc->is_jmp = DISAS_UPDATE; } #endif } @@ -802,7 +807,7 @@ static void gen_exception(DisasContext *dc, uint32_t excp) tcg_gen_movi_tl(cpu_R[R_PC], dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); - dc->is_jmp = DISAS_UPDATE; + dc->is_jmp = DISAS_NORETURN; } /* generate intermediate code for basic block 'tb'. */ @@ -865,6 +870,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) /* Indicate where the next block should start */ switch (dc->is_jmp) { case DISAS_NEXT: + case DISAS_UPDATE: /* Save the current PC back into the CPU register */ tcg_gen_movi_tl(cpu_R[R_PC], dc->pc); tcg_gen_exit_tb(NULL, 0); @@ -872,11 +878,11 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) default: case DISAS_JUMP: - case DISAS_UPDATE: /* The jump will already have updated the PC register */ tcg_gen_exit_tb(NULL, 0); break; + case DISAS_NORETURN: case DISAS_TB_JUMP: /* nothing more to generate */ break; |