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| author | Max Chou <max.chou@sifive.com> | 2023-11-30 01:03:58 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-01-10 18:47:46 +1000 |
| commit | 79fc6d38a819cd30e578023a231385f63583eafb (patch) | |
| tree | 41c08fc9aaf5bc624f9e4c7d79e722805e7dff05 /target | |
| parent | 4eff52cd463e5d130a73bd16d81787c36acc0ec7 (diff) | |
| download | focaccia-qemu-79fc6d38a819cd30e578023a231385f63583eafb.tar.gz focaccia-qemu-79fc6d38a819cd30e578023a231385f63583eafb.zip | |
target/riscv: The whole vector register move instructions depend on vsew
The RISC-V v spec 16.6 section says that the whole vector register move instructions operate as if EEW=SEW. So it should depends on the vsew field of vtype register. Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20231129170400.21251-3-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 114ad87397..3871f0ea73 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3643,8 +3643,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ QEMU_IS_ALIGNED(a->rs2, LEN)) { \ uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN; \ if (s->vstart_eq_zero) { \ - /* EEW = 8 */ \ - tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \ + tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), \ vreg_ofs(s, a->rs2), maxsz, maxsz); \ mark_vs_dirty(s); \ } else { \ |