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| author | LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | 2024-01-30 19:09:45 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-02-09 20:43:14 +1000 |
| commit | ac8c8b6d1e5618f8fd293d9e451d87fb0d3867b3 (patch) | |
| tree | c8453a0354fedcdb9e19af06ba38fb3c7917f335 /target | |
| parent | 1563cdb439e93a37c9bf8570ed80abc3a429d71b (diff) | |
| download | focaccia-qemu-ac8c8b6d1e5618f8fd293d9e451d87fb0d3867b3.tar.gz focaccia-qemu-ac8c8b6d1e5618f8fd293d9e451d87fb0d3867b3.zip | |
target/riscv: FCSR doesn't contain vxrm and vxsat
vxrm and vxsat have been moved into a special register vcsr since RVV v1.0. So remove them from FCSR for vector 1.0. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240130110945.486-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu_bits.h | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 3296648a1f..fc2068ee4d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -32,14 +32,6 @@ #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) -/* Vector Fixed-Point round model */ -#define FSR_VXRM_SHIFT 9 -#define FSR_VXRM (0x3 << FSR_VXRM_SHIFT) - -/* Vector Fixed-Point saturation flag */ -#define FSR_VXSAT_SHIFT 8 -#define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT) - /* Control and Status Registers */ /* User Trap Setup */ |