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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-03-02 10:45:46 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-03-02 10:45:46 +0000 |
| commit | 9f1750ed68911bef069b5d9ba5cef8150972bcf1 (patch) | |
| tree | 7e575e2c9be6f8c74f378e70a4c0e4ec1881dc81 /tcg/arm/tcg-target.inc.c | |
| parent | a4c7ed8b89e8919ddb71c78c4f42b8fdc455ac27 (diff) | |
| parent | 600e17b261555c56a048781b8dd5ba3985650013 (diff) | |
| download | focaccia-qemu-9f1750ed68911bef069b5d9ba5cef8150972bcf1.tar.gz focaccia-qemu-9f1750ed68911bef069b5d9ba5cef8150972bcf1.zip | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200228' into staging
Fix race in cpu_exec_step_atomic. Work around compile failure with -fno-inine. Expand tcg/arm epilogue inline. Adjustments to the default code gen buffer size. # gpg: Signature made Sat 29 Feb 2020 02:13:43 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20200228: accel/tcg: increase default code gen buffer size for 64 bit accel/tcg: only USE_STATIC_CODE_GEN_BUFFER on 32 bit hosts accel/tcg: remove link between guest ram and TCG cache size accel/tcg: use units.h for defining code gen buffer sizes tcg/arm: Expand epilogue inline tcg/arm: Split out tcg_out_epilogue compiler.h: Don't use compile-time assert when __NO_INLINE__ is defined accel/tcg: fix race in cpu_exec_step_atomic (bug 1863025) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tcg/arm/tcg-target.inc.c')
| -rw-r--r-- | tcg/arm/tcg-target.inc.c | 29 |
1 files changed, 12 insertions, 17 deletions
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index fffb6611e2..6aa7757aac 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1745,7 +1745,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) #endif } -static tcg_insn_unit *tb_ret_addr; +static void tcg_out_epilogue(TCGContext *s); static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) @@ -1755,14 +1755,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, switch (opc) { case INDEX_op_exit_tb: - /* Reuse the zeroing that exists for goto_ptr. */ - a0 = args[0]; - if (a0 == 0) { - tcg_out_goto(s, COND_AL, s->code_gen_epilogue); - } else { - tcg_out_movi32(s, COND_AL, TCG_REG_R0, args[0]); - tcg_out_goto(s, COND_AL, tb_ret_addr); - } + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, args[0]); + tcg_out_epilogue(s); break; case INDEX_op_goto_tb: { @@ -2284,19 +2278,17 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count) + TCG_TARGET_STACK_ALIGN - 1) \ & -TCG_TARGET_STACK_ALIGN) +#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) + static void tcg_target_qemu_prologue(TCGContext *s) { - int stack_addend; - /* Calling convention requires us to save r4-r11 and lr. */ /* stmdb sp!, { r4 - r11, lr } */ tcg_out32(s, (COND_AL << 28) | 0x092d4ff0); /* Reserve callee argument and tcg temp space. */ - stack_addend = FRAME_SIZE - PUSH_SIZE; - tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, - TCG_REG_CALL_STACK, stack_addend, 1); + TCG_REG_CALL_STACK, STACK_ADDEND, 1); tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, CPU_TEMP_BUF_NLONGS * sizeof(long)); @@ -2310,11 +2302,14 @@ static void tcg_target_qemu_prologue(TCGContext *s) */ s->code_gen_epilogue = s->code_ptr; tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); + tcg_out_epilogue(s); +} - /* TB epilogue */ - tb_ret_addr = s->code_ptr; +static void tcg_out_epilogue(TCGContext *s) +{ + /* Release local stack frame. */ tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, - TCG_REG_CALL_STACK, stack_addend, 1); + TCG_REG_CALL_STACK, STACK_ADDEND, 1); /* ldmia sp!, { r4 - r11, pc } */ tcg_out32(s, (COND_AL << 28) | 0x08bd8ff0); |