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| author | Richard Henderson <rth@twiddle.net> | 2013-03-11 18:04:14 -0700 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2013-04-27 02:16:43 +0200 |
| commit | d9fda57549877045aa0ec91d2a067a67cb41a29f (patch) | |
| tree | 39a996fc26a69f86cb5a3eb83bc316c41d58ed52 /tcg/arm | |
| parent | a9a86ae95d24c587285856405dffc9cacdf2b683 (diff) | |
| download | focaccia-qemu-d9fda57549877045aa0ec91d2a067a67cb41a29f.tar.gz focaccia-qemu-d9fda57549877045aa0ec91d2a067a67cb41a29f.zip | |
tcg-arm: Allow constant first argument to sub
This allows the generation of RSB instructions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/arm')
| -rw-r--r-- | tcg/arm/tcg-target.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index de8465bc49..6c7113b471 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1625,8 +1625,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, args[0], args[1], args[2], const_args[2]); break; case INDEX_op_sub_i32: - tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, - args[0], args[1], args[2], const_args[2]); + if (const_args[1]) { + if (const_args[2]) { + tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); + } else { + tcg_out_dat_rI(s, COND_AL, ARITH_RSB, + args[0], args[2], args[1], 1); + } + } else { + tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, + args[0], args[1], args[2], const_args[2]); + } break; case INDEX_op_and_i32: tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, @@ -1819,7 +1828,7 @@ static const TCGTargetOpDef arm_op_defs[] = { /* TODO: "r", "r", "ri" */ { INDEX_op_add_i32, { "r", "r", "rIN" } }, - { INDEX_op_sub_i32, { "r", "r", "rIN" } }, + { INDEX_op_sub_i32, { "r", "rI", "rIN" } }, { INDEX_op_mul_i32, { "r", "r", "r" } }, { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } }, { INDEX_op_muls2_i32, { "r", "r", "r", "r" } }, |