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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-01-26 17:34:19 -0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-04-28 13:40:17 -0700 |
| commit | 33aba058c8fcc9b1581b03a1fbac45d8d91baac6 (patch) | |
| tree | a453866d9fc6c2660be86004709a13cb2b28ebd1 /tcg/i386/tcg-target.c.inc | |
| parent | bf7ca5fb3032b95fd83dbb9883e904ee28baa229 (diff) | |
| download | focaccia-qemu-33aba058c8fcc9b1581b03a1fbac45d8d91baac6.tar.gz focaccia-qemu-33aba058c8fcc9b1581b03a1fbac45d8d91baac6.zip | |
tcg: Remove INDEX_op_qemu_st8_*
The i386 backend can now check TCGOP_FLAGS to select the correct set of constraints. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/i386/tcg-target.c.inc')
| -rw-r--r-- | tcg/i386/tcg-target.c.inc | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 52285bcd54..6c4c2ebd0e 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2457,7 +2457,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, switch (memop & MO_SIZE) { case MO_8: - /* This is handled with constraints on INDEX_op_qemu_st8_i32. */ + /* This is handled with constraints on INDEX_op_qemu_st_i32. */ tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || datalo < 4); tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + h.seg, datalo, h.base, h.index, 0, h.ofs); @@ -3568,7 +3568,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, break; case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st8_i32: tcg_out_qemu_st(s, a0, -1, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_st_i64: @@ -4140,9 +4139,9 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) return C_O1_I1(r, L); case INDEX_op_qemu_st_i32: - return C_O0_I2(L, L); - case INDEX_op_qemu_st8_i32: - return C_O0_I2(s, L); + return (TCG_TARGET_REG_BITS == 32 && flags == MO_8 + ? C_O0_I2(s, L) + : C_O0_I2(L, L)); case INDEX_op_qemu_ld_i64: return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O2_I1(r, r, L); |