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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-12-09 13:58:39 -0600 |
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| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-01-07 05:09:06 -1000 |
| commit | 07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1 (patch) | |
| tree | a22f2b213b2cb96c8e0e30c69bca9edb00b678bc /tcg/optimize.c | |
| parent | d2ef1b83a7a2047e0e36d7b62b3a5d151ab958f5 (diff) | |
| download | focaccia-qemu-07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1.tar.gz focaccia-qemu-07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1.zip | |
tcg: Introduce INDEX_op_qemu_st8_i32
Enable this on i386 to restrict the set of input registers for an 8-bit store, as required by the architecture. This removes the last use of scratch registers for user-only mode. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/optimize.c')
| -rw-r--r-- | tcg/optimize.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tcg/optimize.c b/tcg/optimize.c index 7ca71de956..1fb42eb2a9 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1541,6 +1541,7 @@ void tcg_optimize(TCGContext *s) case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st8_i32: case INDEX_op_qemu_st_i64: case INDEX_op_call: /* Opcodes that touch guest memory stop the optimization. */ |