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| author | Richard Henderson <rth@twiddle.net> | 2013-08-14 14:46:08 -0700 |
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| committer | Richard Henderson <rth@twiddle.net> | 2013-09-02 09:08:29 -0700 |
| commit | 32f5717f07e5f801e482052311d21a4223fc78f1 (patch) | |
| tree | 4838bdf1a8a2b37730a1de0f549dd6f816d121bf /tcg/optimize.c | |
| parent | 3c9a8f17560794ad23889318cc42894c6e592cc3 (diff) | |
| download | focaccia-qemu-32f5717f07e5f801e482052311d21a4223fc78f1.tar.gz focaccia-qemu-32f5717f07e5f801e482052311d21a4223fc78f1.zip | |
tcg-ppc64: Implement muluh, mulsh
Using these instead of mulu2 and muls2 lets us avoid having to argument overlap analysis in the backend. Normal register allocation will DTRT. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/optimize.c')
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