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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-08-08 10:39:18 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-08-08 10:39:18 +0100 |
| commit | cf5198d58088e3b416fe517b3946e5120b342761 (patch) | |
| tree | 9d90c54eca81527f3f423e2daf7b29eccc32a35e /tcg/optimize.c | |
| parent | 51009170d8fc263cfdcd5a60fe3ba213daa3d15b (diff) | |
| parent | 5a18407f55ade924aa6397c9a043a9ffd59645fe (diff) | |
| download | focaccia-qemu-cf5198d58088e3b416fe517b3946e5120b342761.tar.gz focaccia-qemu-cf5198d58088e3b416fe517b3946e5120b342761.zip | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20160805' into staging
indirect register lowering # gpg: Signature made Fri 05 Aug 2016 17:34:53 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20160805: tcg: Lower indirect registers in a separate pass tcg: Require liveness analysis tcg: Include liveness info in the dumps tcg: Compress dead_temps and mem_temps into a single array tcg: Fold life data into TCGOp tcg: Reorg TCGOp chaining tcg: Compress liveness data to 16 bits Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tcg/optimize.c')
| -rw-r--r-- | tcg/optimize.c | 37 |
1 files changed, 3 insertions, 34 deletions
diff --git a/tcg/optimize.c b/tcg/optimize.c index c0d975b3d9..cffe89b525 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -82,37 +82,6 @@ static void init_temp_info(TCGArg temp) } } -static TCGOp *insert_op_before(TCGContext *s, TCGOp *old_op, - TCGOpcode opc, int nargs) -{ - int oi = s->gen_next_op_idx; - int pi = s->gen_next_parm_idx; - int prev = old_op->prev; - int next = old_op - s->gen_op_buf; - TCGOp *new_op; - - tcg_debug_assert(oi < OPC_BUF_SIZE); - tcg_debug_assert(pi + nargs <= OPPARAM_BUF_SIZE); - s->gen_next_op_idx = oi + 1; - s->gen_next_parm_idx = pi + nargs; - - new_op = &s->gen_op_buf[oi]; - *new_op = (TCGOp){ - .opc = opc, - .args = pi, - .prev = prev, - .next = next - }; - if (prev >= 0) { - s->gen_op_buf[prev].next = oi; - } else { - s->gen_first_op_idx = oi; - } - old_op->prev = oi; - - return new_op; -} - static int op_bits(TCGOpcode op) { const TCGOpDef *def = &tcg_op_defs[op]; @@ -583,7 +552,7 @@ void tcg_optimize(TCGContext *s) nb_globals = s->nb_globals; reset_all_temps(nb_temps); - for (oi = s->gen_first_op_idx; oi >= 0; oi = oi_next) { + for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) { tcg_target_ulong mask, partmask, affected; int nb_oargs, nb_iargs, i; TCGArg tmp; @@ -1120,7 +1089,7 @@ void tcg_optimize(TCGContext *s) uint64_t a = ((uint64_t)ah << 32) | al; uint64_t b = ((uint64_t)bh << 32) | bl; TCGArg rl, rh; - TCGOp *op2 = insert_op_before(s, op, INDEX_op_movi_i32, 2); + TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32, 2); TCGArg *args2 = &s->gen_opparam_buf[op2->args]; if (opc == INDEX_op_add2_i32) { @@ -1146,7 +1115,7 @@ void tcg_optimize(TCGContext *s) uint32_t b = temps[args[3]].val; uint64_t r = (uint64_t)a * b; TCGArg rl, rh; - TCGOp *op2 = insert_op_before(s, op, INDEX_op_movi_i32, 2); + TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32, 2); TCGArg *args2 = &s->gen_opparam_buf[op2->args]; rl = args[0]; |