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| author | Aurelien Jarno <aurelien@aurel32.net> | 2013-09-03 08:27:38 +0200 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2014-02-17 10:12:28 -0600 |
| commit | e46b225a3137e62c975c49aaae7bb5f9583cc428 (patch) | |
| tree | aba700db46bf9759e561945e7b4b753c27db4e80 /tcg/optimize.c | |
| parent | 7a3a00979d9dfe2aaa66ce5fc68cd161b4f900ba (diff) | |
| download | focaccia-qemu-e46b225a3137e62c975c49aaae7bb5f9583cc428.tar.gz focaccia-qemu-e46b225a3137e62c975c49aaae7bb5f9583cc428.zip | |
tcg/optimize: fix known-zero bits for right shift ops
32-bit versions of sar and shr ops should not propagate known-zero bits from the unused 32 high bits. For sar it could even lead to wrong code being generated. Cc: qemu-stable@nongnu.org Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/optimize.c')
| -rw-r--r-- | tcg/optimize.c | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/tcg/optimize.c b/tcg/optimize.c index 89e2d6a3b3..c5cdde2160 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -726,16 +726,25 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, mask = temps[args[1]].mask & mask; break; - CASE_OP_32_64(sar): + case INDEX_op_sar_i32: + if (temps[args[2]].state == TCG_TEMP_CONST) { + mask = (int32_t)temps[args[1]].mask >> temps[args[2]].val; + } + break; + case INDEX_op_sar_i64: if (temps[args[2]].state == TCG_TEMP_CONST) { - mask = ((tcg_target_long)temps[args[1]].mask - >> temps[args[2]].val); + mask = (int64_t)temps[args[1]].mask >> temps[args[2]].val; } break; - CASE_OP_32_64(shr): + case INDEX_op_shr_i32: + if (temps[args[2]].state == TCG_TEMP_CONST) { + mask = (uint32_t)temps[args[1]].mask >> temps[args[2]].val; + } + break; + case INDEX_op_shr_i64: if (temps[args[2]].state == TCG_TEMP_CONST) { - mask = temps[args[1]].mask >> temps[args[2]].val; + mask = (uint64_t)temps[args[1]].mask >> temps[args[2]].val; } break; |