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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-01-06 12:26:28 -0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-04-28 13:40:15 -0700 |
| commit | a341c84e8153b7282b083e871ca534f15fa70898 (patch) | |
| tree | 3627fcac94cfe78912444d14bfd0c2231ab75fa9 /tcg/riscv/tcg-target-has.h | |
| parent | 93a9ddb84ae534a04e8d7764caa9e29b8285b2b1 (diff) | |
| download | focaccia-qemu-a341c84e8153b7282b083e871ca534f15fa70898.tar.gz focaccia-qemu-a341c84e8153b7282b083e871ca534f15fa70898.zip | |
tcg: Convert andc to TCGOutOpBinary
At the same time, drop all backend support for immediate operands, as we now transform andc to and during optimize. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/riscv/tcg-target-has.h')
| -rw-r--r-- | tcg/riscv/tcg-target-has.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h index fc62049c78..a3918bf7f5 100644 --- a/tcg/riscv/tcg-target-has.h +++ b/tcg/riscv/tcg-target-has.h @@ -25,7 +25,6 @@ #define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_andc_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_orc_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_eqv_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_nand_i32 0 @@ -46,7 +45,6 @@ #define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_not_i64 1 -#define TCG_TARGET_HAS_andc_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_orc_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_eqv_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_nand_i64 0 |