diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2024-12-29 20:52:12 -0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-01-16 20:57:17 -0800 |
| commit | fa65f13555e121566c9105f252c72a3b63f1ecea (patch) | |
| tree | 6e6fe34c6cd8850170cd13f9a1e89a7c2ea428f5 /tcg/riscv/tcg-target.c.inc | |
| parent | 841e2c5257102c738e8578eb0ce38d3de830ea4c (diff) | |
| download | focaccia-qemu-fa65f13555e121566c9105f252c72a3b63f1ecea.tar.gz focaccia-qemu-fa65f13555e121566c9105f252c72a3b63f1ecea.zip | |
tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64
Extracts which abut bit 32 may use 32-bit shifts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/riscv/tcg-target.c.inc')
| -rw-r--r-- | tcg/riscv/tcg-target.c.inc | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index fc93900c6d..4f6e18f59e 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -2344,8 +2344,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, break; case INDEX_op_extract_i64: - if (a2 == 0 && args[3] == 32) { - tcg_out_ext32u(s, a0, a1); + if (a2 + args[3] == 32) { + if (a2 == 0) { + tcg_out_ext32u(s, a0, a1); + } else { + tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2); + } break; } /* FALLTHRU */ @@ -2358,8 +2362,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, break; case INDEX_op_sextract_i64: - if (a2 == 0 && args[3] == 32) { - tcg_out_ext32s(s, a0, a1); + if (a2 + args[3] == 32) { + if (a2 == 0) { + tcg_out_ext32s(s, a0, a1); + } else { + tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2); + } break; } /* FALLTHRU */ |