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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-12-09 13:58:39 -0600 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-01-07 05:09:06 -1000 |
| commit | 07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1 (patch) | |
| tree | a22f2b213b2cb96c8e0e30c69bca9edb00b678bc /tcg/riscv/tcg-target.h | |
| parent | d2ef1b83a7a2047e0e36d7b62b3a5d151ab958f5 (diff) | |
| download | focaccia-qemu-07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1.tar.gz focaccia-qemu-07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1.zip | |
tcg: Introduce INDEX_op_qemu_st8_i32
Enable this on i386 to restrict the set of input registers for an 8-bit store, as required by the architecture. This removes the last use of scratch registers for user-only mode. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/riscv/tcg-target.h')
| -rw-r--r-- | tcg/riscv/tcg-target.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index c1bd52bb9a..888288d54c 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -119,6 +119,7 @@ typedef enum { #define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_brcond2 1 #define TCG_TARGET_HAS_setcond2 1 +#define TCG_TARGET_HAS_qemu_st8_i32 0 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_movcond_i64 0 |