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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-05-01 10:57:11 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-06-05 12:04:28 -0700 |
| commit | d46259c037e51fb6516199305fe8f0994df3d46e (patch) | |
| tree | 4a2cedcb5ce045685b565a0947f5dbb479556c07 /tcg/riscv/tcg-target.h | |
| parent | e5b490637708a688e303a51d47fea3bd14ec98f6 (diff) | |
| download | focaccia-qemu-d46259c037e51fb6516199305fe8f0994df3d46e.tar.gz focaccia-qemu-d46259c037e51fb6516199305fe8f0994df3d46e.zip | |
tcg: Split out tcg-target-reg-bits.h
Often, the only thing we need to know about the TCG host is the register size. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/riscv/tcg-target.h')
| -rw-r--r-- | tcg/riscv/tcg-target.h | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 54fdff0caa..e1d8110ee4 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -25,15 +25,6 @@ #ifndef RISCV_TCG_TARGET_H #define RISCV_TCG_TARGET_H -/* - * We don't support oversize guests. - * Since we will only build tcg once, this in turn requires a 64-bit host. - */ -#if __riscv_xlen != 64 -#error "unsupported code generation mode" -#endif -#define TCG_TARGET_REG_BITS 64 - #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_NB_REGS 32 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) |