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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-07-09 11:49:26 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-07-09 11:49:26 +0100 |
| commit | a538626aff7c8934ec47bc6ed41cac5bd1b7723c (patch) | |
| tree | fa5d877c4858eeded149428d8ba426f8af5fd12a /tcg/riscv/tcg-target.inc.c | |
| parent | f34edbc760b0f689deddd175fc08732ecb46665f (diff) | |
| parent | 11978f6f58f1d3d66429f7ff897524f693d823ce (diff) | |
| download | focaccia-qemu-a538626aff7c8934ec47bc6ed41cac5bd1b7723c.tar.gz focaccia-qemu-a538626aff7c8934ec47bc6ed41cac5bd1b7723c.zip | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190709' into staging
Minor gvec fix for as-yet uncommitted altivec host. Build fix for riscv host. # gpg: Signature made Tue 09 Jul 2019 07:27:34 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190709: tcg: Fix expansion of INDEX_op_not_vec tcg/riscv: Fix RISC-VH host build failure Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tcg/riscv/tcg-target.inc.c')
| -rw-r--r-- | tcg/riscv/tcg-target.inc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 1f0ae64aae..3e76bf5738 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -980,8 +980,8 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |