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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-04-05 18:56:28 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-04-23 08:46:45 +0100 |
| commit | b9bfe000f954e1defefb4c917f98bf82c337144b (patch) | |
| tree | 681e36737e9a936a5c9a3213aa57c91b44478153 /tcg/sparc64 | |
| parent | 9c6aa274a494ce807e998a3652fa16a3d2da4387 (diff) | |
| download | focaccia-qemu-b9bfe000f954e1defefb4c917f98bf82c337144b.tar.gz focaccia-qemu-b9bfe000f954e1defefb4c917f98bf82c337144b.zip | |
tcg: Split out tcg_out_extu_i32_i64
We will need a backend interface for type extension with zero. Use it in tcg_reg_alloc_op in the meantime. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/sparc64')
| -rw-r--r-- | tcg/sparc64/tcg-target.c.inc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 56ffc6ed91..c57a8c8304 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -532,6 +532,11 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) tcg_out_ext32s(s, rd, rs); } +static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_ext32u(s, rd, rs); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -1682,9 +1687,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_divu_i64: c = ARITH_UDIVX; goto gen_arith; - case INDEX_op_extu_i32_i64: - tcg_out_ext32u(s, a0, a1); - break; case INDEX_op_extrl_i64_i32: tcg_out_mov(s, TCG_TYPE_I32, a0, a1); break; @@ -1741,6 +1743,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: default: g_assert_not_reached(); } |