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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-10-08 17:18:46 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-10-08 17:18:46 +0100 |
| commit | e64cf4d569f6461d6b9072e00d6e78d0ab8bd4a7 (patch) | |
| tree | efbcd66a45366ea73298f67075b07f7cd203c269 /tcg/tcg-op-vec.c | |
| parent | a1d22c668a7662289b42624fe2aa92c9a23df1d2 (diff) | |
| parent | 62475e9d007d83db4d0a6ccebcda8914f392e9c9 (diff) | |
| download | focaccia-qemu-e64cf4d569f6461d6b9072e00d6e78d0ab8bd4a7.tar.gz focaccia-qemu-e64cf4d569f6461d6b9072e00d6e78d0ab8bd4a7.zip | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20201008' into staging
Extend maximum gvec vector size Fix i386 avx2 dupi Fix mips host user-only write detection Misc cleanups. # gpg: Signature made Thu 08 Oct 2020 13:55:22 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20201008: accel/tcg: Fix computing of is_write for MIPS tcg: Remove TCG_TARGET_HAS_cmp_vec tcg/optimize: Fold dup2_vec tcg: Fix generation of dupi_vec for 32-bit host tcg/i386: Fix dupi for avx2 32-bit hosts tcg: Remove TCGOpDef.used tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields tcg: Remove TCG_CT_REG tcg: Move sorted_args into TCGArgConstraint.sort_index tcg: Drop union from TCGArgConstraint tcg: Adjust simd_desc size encoding Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tcg/tcg-op-vec.c')
| -rw-r--r-- | tcg/tcg-op-vec.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index ed6fb55fe1..cdbf11c573 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -252,10 +252,10 @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m) void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a) { - if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) { - do_dupi_vec(r, MO_32, a); - } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) { + if (TCG_TARGET_REG_BITS == 64) { do_dupi_vec(r, MO_64, a); + } else if (a == dup_const(MO_32, a)) { + do_dupi_vec(r, MO_32, a); } else { TCGv_i64 c = tcg_const_i64(a); tcg_gen_dup_i64_vec(MO_64, r, c); @@ -280,7 +280,11 @@ void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a) void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a) { - do_dupi_vec(r, MO_REG, dup_const(vece, a)); + if (vece == MO_64) { + tcg_gen_dup64i_vec(r, a); + } else { + do_dupi_vec(r, MO_REG, dup_const(vece, a)); + } } void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a) |