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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-09-16 16:54:50 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-09-16 16:54:50 +0100 |
| commit | e3571ae30cd26d19efd4554c25e32ef64d6a36b3 (patch) | |
| tree | b753d7c12df7c6c955bc93e3947c97cd7428125b /tcg/tcg-opc.h | |
| parent | ebc231d7daf1f41b23d8b6a6d1234800b86e5fe2 (diff) | |
| parent | 34f939218ce78163171addd63750e1e0300376ab (diff) | |
| download | focaccia-qemu-e3571ae30cd26d19efd4554c25e32ef64d6a36b3.tar.gz focaccia-qemu-e3571ae30cd26d19efd4554c25e32ef64d6a36b3.zip | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20160916' into staging
tcg queued patches # gpg: Signature made Fri 16 Sep 2016 16:14:20 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20160916: tcg: Optimize fence instructions target-i386: Generate fences for x86 target-aarch64: Generate fences for aarch64 target-arm: Generate fences in ARMv7 frontend target-alpha: Generate fence op tcg/tci: Add support for fence tcg/sparc: Add support for fence tcg/s390: Add support for fence tcg/ppc: Add support for fence tcg/mips: Add support for fence tcg/ia64: Add support for fence tcg/arm: Add support for fence tcg/aarch64: Add support for fence tcg/i386: Add support for fence Introduce TCGOpcode for memory barrier cpu-exec: Check -dfilter for -d cpu tcg: Merge GETPC and GETRA tcg: Support arbitrary size + alignment Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tcg/tcg-opc.h')
| -rw-r--r-- | tcg/tcg-opc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 6d0410c4b9..45528d2192 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -42,6 +42,8 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END) # define IMPL64 TCG_OPF_64BIT #endif +DEF(mb, 0, 0, 1, 0) + DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) DEF(setcond_i32, 1, 2, 1, 0) |