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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-08-04 23:24:04 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-08-24 11:22:42 -0700 |
| commit | 3635502dd00bcfee3a6ab790d950c2fc4ace607b (patch) | |
| tree | d3a3f2e187d586a23b33af696d3c24dd11a8a114 /tcg/tcg.c | |
| parent | 13d885b0ad4ada4d216b0341de5ae4a9ce3f5abb (diff) | |
| download | focaccia-qemu-3635502dd00bcfee3a6ab790d950c2fc4ace607b.tar.gz focaccia-qemu-3635502dd00bcfee3a6ab790d950c2fc4ace607b.zip | |
tcg: Introduce negsetcond opcodes
Introduce a new opcode for negative setcond. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tcg.c')
| -rw-r--r-- | tcg/tcg.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/tcg/tcg.c b/tcg/tcg.c index a23348824b..620dbe08da 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1879,6 +1879,8 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_sar_i32: return true; + case INDEX_op_negsetcond_i32: + return TCG_TARGET_HAS_negsetcond_i32; case INDEX_op_movcond_i32: return TCG_TARGET_HAS_movcond_i32; case INDEX_op_div_i32: @@ -1977,6 +1979,8 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_extu_i32_i64: return TCG_TARGET_REG_BITS == 64; + case INDEX_op_negsetcond_i64: + return TCG_TARGET_HAS_negsetcond_i64; case INDEX_op_movcond_i64: return TCG_TARGET_HAS_movcond_i64; case INDEX_op_div_i64: @@ -2509,11 +2513,13 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs) switch (c) { case INDEX_op_brcond_i32: case INDEX_op_setcond_i32: + case INDEX_op_negsetcond_i32: case INDEX_op_movcond_i32: case INDEX_op_brcond2_i32: case INDEX_op_setcond2_i32: case INDEX_op_brcond_i64: case INDEX_op_setcond_i64: + case INDEX_op_negsetcond_i64: case INDEX_op_movcond_i64: case INDEX_op_cmp_vec: case INDEX_op_cmpsel_vec: |