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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-01-07 22:52:10 -0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-04-28 13:40:16 -0700 |
| commit | 74dbd36f1f87bd7fc4705644d63c5561a23b0567 (patch) | |
| tree | f5f6617c709934260e47c8f165bafdcc6470c501 /tcg/tci.c | |
| parent | edd6ba8a6bc804153a8fe643a7e2dae0802db98c (diff) | |
| download | focaccia-qemu-74dbd36f1f87bd7fc4705644d63c5561a23b0567.tar.gz focaccia-qemu-74dbd36f1f87bd7fc4705644d63c5561a23b0567.zip | |
tcg: Merge INDEX_op_shr_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tci.c')
| -rw-r--r-- | tcg/tci.c | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/tcg/tci.c b/tcg/tci.c index 22401ce1f6..376b1b1ece 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -621,9 +621,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] << (regs[r2] % TCG_TARGET_REG_BITS); break; - case INDEX_op_shr_i32: + case INDEX_op_shr: tci_args_rrr(insn, &r0, &r1, &r2); - regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31); + regs[r0] = regs[r1] >> (regs[r2] % TCG_TARGET_REG_BITS); break; case INDEX_op_sar_i32: tci_args_rrr(insn, &r0, &r1, &r2); @@ -787,10 +787,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Shift/rotate operations (64 bit). */ - case INDEX_op_shr_i64: - tci_args_rrr(insn, &r0, &r1, &r2); - regs[r0] = regs[r1] >> (regs[r2] & 63); - break; case INDEX_op_sar_i64: tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63); @@ -1078,10 +1074,9 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_rems: case INDEX_op_remu: case INDEX_op_shl: + case INDEX_op_shr: case INDEX_op_sub: case INDEX_op_xor: - case INDEX_op_shr_i32: - case INDEX_op_shr_i64: case INDEX_op_sar_i32: case INDEX_op_sar_i64: case INDEX_op_rotl_i32: |