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| author | Blue Swirl <blauwirbel@gmail.com> | 2011-11-19 11:17:58 +0000 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2011-11-19 11:17:58 +0000 |
| commit | 25cc4a768d91817bc3b4bf9b3a270c4791509cd7 (patch) | |
| tree | 78a65c66213c777fd87d68192ab82bc0f80b6d1e /tci.c | |
| parent | 05a86f23e5ca83348eface349429341cefb8697b (diff) | |
| parent | 326384d5b6dcea69ca44695ee807f8b50234ab71 (diff) | |
| download | focaccia-qemu-25cc4a768d91817bc3b4bf9b3a270c4791509cd7.tar.gz focaccia-qemu-25cc4a768d91817bc3b4bf9b3a270c4791509cd7.zip | |
Merge branch 's390-1.0' of git://repo.or.cz/qemu/agraf
* 's390-1.0' of git://repo.or.cz/qemu/agraf: s390x: initialize virtio dev region tcg: Use TCGReg for standard tcg-target entry points. tcg: Standardize on TCGReg as the enum for hard registers s390x: Add shutdown for TCG s390-virtio machine s390: Fix cpu shutdown for KVM s390: fix short kernel command lines s390: fix reset hypercall to reset the status s390x: implement SIGP restart and shutdown s390x: implement rrbe instruction properly s390x: update R and C bits in storage key s390x: make ipte 31-bit aware s390x: add ldeb instruction
Diffstat (limited to 'tci.c')
| -rw-r--r-- | tci.c | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/tci.c b/tci.c index f17785dc98..a20a7142ed 100644 --- a/tci.c +++ b/tci.c @@ -63,90 +63,90 @@ void *tci_tb_ptr; static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS]; -static tcg_target_ulong tci_read_reg(TCGRegister index) +static tcg_target_ulong tci_read_reg(TCGReg index) { assert(index < ARRAY_SIZE(tci_reg)); return tci_reg[index]; } #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -static int8_t tci_read_reg8s(TCGRegister index) +static int8_t tci_read_reg8s(TCGReg index) { return (int8_t)tci_read_reg(index); } #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -static int16_t tci_read_reg16s(TCGRegister index) +static int16_t tci_read_reg16s(TCGReg index) { return (int16_t)tci_read_reg(index); } #endif #if TCG_TARGET_REG_BITS == 64 -static int32_t tci_read_reg32s(TCGRegister index) +static int32_t tci_read_reg32s(TCGReg index) { return (int32_t)tci_read_reg(index); } #endif -static uint8_t tci_read_reg8(TCGRegister index) +static uint8_t tci_read_reg8(TCGReg index) { return (uint8_t)tci_read_reg(index); } -static uint16_t tci_read_reg16(TCGRegister index) +static uint16_t tci_read_reg16(TCGReg index) { return (uint16_t)tci_read_reg(index); } -static uint32_t tci_read_reg32(TCGRegister index) +static uint32_t tci_read_reg32(TCGReg index) { return (uint32_t)tci_read_reg(index); } #if TCG_TARGET_REG_BITS == 64 -static uint64_t tci_read_reg64(TCGRegister index) +static uint64_t tci_read_reg64(TCGReg index) { return tci_read_reg(index); } #endif -static void tci_write_reg(TCGRegister index, tcg_target_ulong value) +static void tci_write_reg(TCGReg index, tcg_target_ulong value) { assert(index < ARRAY_SIZE(tci_reg)); assert(index != TCG_AREG0); tci_reg[index] = value; } -static void tci_write_reg8s(TCGRegister index, int8_t value) +static void tci_write_reg8s(TCGReg index, int8_t value) { tci_write_reg(index, value); } -static void tci_write_reg16s(TCGRegister index, int16_t value) +static void tci_write_reg16s(TCGReg index, int16_t value) { tci_write_reg(index, value); } #if TCG_TARGET_REG_BITS == 64 -static void tci_write_reg32s(TCGRegister index, int32_t value) +static void tci_write_reg32s(TCGReg index, int32_t value) { tci_write_reg(index, value); } #endif -static void tci_write_reg8(TCGRegister index, uint8_t value) +static void tci_write_reg8(TCGReg index, uint8_t value) { tci_write_reg(index, value); } -static void tci_write_reg16(TCGRegister index, uint16_t value) +static void tci_write_reg16(TCGReg index, uint16_t value) { tci_write_reg(index, value); } -static void tci_write_reg32(TCGRegister index, uint32_t value) +static void tci_write_reg32(TCGReg index, uint32_t value) { tci_write_reg(index, value); } @@ -159,7 +159,7 @@ static void tci_write_reg64(uint32_t high_index, uint32_t low_index, tci_write_reg(high_index, value >> 32); } #elif TCG_TARGET_REG_BITS == 64 -static void tci_write_reg64(TCGRegister index, uint64_t value) +static void tci_write_reg64(TCGReg index, uint64_t value) { tci_write_reg(index, value); } @@ -290,7 +290,7 @@ static target_ulong tci_read_ulong(uint8_t **tb_ptr) static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) { tcg_target_ulong value; - TCGRegister r = **tb_ptr; + TCGReg r = **tb_ptr; *tb_ptr += 1; if (r == TCG_CONST) { value = tci_read_i(tb_ptr); @@ -304,7 +304,7 @@ static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) static uint32_t tci_read_ri32(uint8_t **tb_ptr) { uint32_t value; - TCGRegister r = **tb_ptr; + TCGReg r = **tb_ptr; *tb_ptr += 1; if (r == TCG_CONST) { value = tci_read_i32(tb_ptr); @@ -326,7 +326,7 @@ static uint64_t tci_read_ri64(uint8_t **tb_ptr) static uint64_t tci_read_ri64(uint8_t **tb_ptr) { uint64_t value; - TCGRegister r = **tb_ptr; + TCGReg r = **tb_ptr; *tb_ptr += 1; if (r == TCG_CONST) { value = tci_read_i64(tb_ptr); |